In organic chip packages, coefficient of thermal expansion (CTE) mismatch, i.e., the mismatch which occurs in the chip plus carrier system, can cause significant warping of the chip package. Typically, the mismatch can be caused when the package flexes substantially from temperature changes which occur during assembly and use. The flexing also results from, among other things, stresses and strains generated in the chips, in the underfill and laminate materials used in the package, and in the thermal interface material (TIM). CTE mismatch can also result from bottom surface metallurgy (BSM) coplanarity, and ball grid array (BGA) and land grid array (LGA) contact uniformity.
Multi-chip packages can exacerbate CTE mismatch since they also produce warping and stresses. These typically result from the additional silicon area of such packages, inherent asymmetries created in the packages, and the greater spans utilized between the silicon and lid seal area. Multi-chip packages also have thermal issues relating to TIM bond line control which result from multiple device heights.
High-end processor packages also suffer from CTE mismatch because they have more demanding thermal requirements requiring high power dissipation and multi-core chips with high heat flux areas. They also require thin bond line with high performance TIM.
Some current industry solutions for multi-chip organic packages include the Intel dual chip LGA organic package with thick Indium TIM on both chips. This solution, however, is expensive. The Microsoft GPU dual chip low-power package utilizes different chip heights, a Chomerics T-577 phase change material on both chips, and direct heat sink attachment.
It is also notable that the difference in the coefficient of thermal expansion in organic module packages between the silicon (3 ppm) on the chip and the organic carrier, which is mainly copper with some thin organic layers, (15 ppm) is very high. When the silicon chip is essentially “locked in” to the carrier during the cure of the epoxy underfill (between 120 and 170 C), the carrier is stretched out more than the silicon. When the assembly cools back to room temperature, the carrier will shrink back more and generate a warped system where the chip is bent so that its outward facing surface is convex.
The additional structures in the module assembly, such as the lid, lid seal, and thermal interface materials (TIM), can be used to control this warped state. By coupling the chip and carrier to a stiffer lid, the warp can be controlled. A warped system has more strain and stress in the different materials and can cause failure.
The warp in a typical organic single chip module package can be controlled by the lid, TIM, and lid seal materials. In cases where a low strength TIM material is used, the lid and lid seal materials provide the majority of warpage control.
Design of multi-chip packages also take into account that the package will typically have greater silicon area and can have some level of asymmetry. This can cause additional stress and strain in the TIM interfaces, and especially in regions between the chips which are located farther from structural support of the lid seal. In the case of high performance packages, a popular solution for multi-chip packages has been to use a solder material as the thermal interface for all the chips within the package. This tends to be expensive, however.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described herein.